Conventional memory systems include a memory controller configured to control memory access to one or more memory devices, such as DRAMs, SRAMs, or Flash memory devices. Memory systems often employ a data strobe signal (DQS) to accompany the read data signal (DQ) being transmitted between the memory controller and the memory device to indicate the point at which the data signal should be sampled or captured. In a memory read operation from the memory device, the memory device drives the data strobe signal and provides the read data on the data signal lines. In particular, during a read operation, the memory device drives the data strobe signal to a logical low level for a preamble period. The read data is provided after the preamble period and the data strobe signal then toggles with the read data. When reading data from the memory device, the data strobe signal edge transitions at the same time as the read data transitions. That is, the data strobe signal generated by the memory device in a read operation is edge-aligned with the data. The memory controller uses the data strobe signal as a reference signal to capture the read data being provided on the data signal lines whereby the data strobe signal is delayed to the center of read data to maximize the valid data window.
In a typical memory system, the memory controller communicates with the memory device over traces formed on the PCB board. The signals transmitted between the memory controller and the memory device are subjected to latency due to the physical layout, the distance of the signal trances and other factors. As a result, there could be delay skew between the data strobe signal and the read data signals from the memory device due to variation in the propagation delays of the signal lines. As received by the memory controller, the data strobe signal and the read data signal transitions may no longer line up. As clock frequencies increases, the delay variation between the data strobe signal and the read data becomes more problematic and may result in the memory controller capturing invalid data or missing capture of valid read data.
Memory read training is a technique often employed in memory systems including high speed memory devices. Memory read training is performed to enable the memory controller to determine the delay offset to use for communicating with the high speed memory device. In particular, memory read training is performed to determine the delay offset the memory controller should use so that the data strobe signal and the data signal are aligned at the memory controller. Memory read training is performed using a predefined read data sequence (“training data”) that is stored in a register of the memory device instead of the memory cell array. In conventional memory systems, memory read training is performing by placing the memory device in a dedicated training mode instead of the normal memory read operation mode. The memory controller writes to certain predefined register to cause the memory device to enter into the training mode and to read the predefined read data sequence from the register, instead of reading data from the memory cell array. With the predefined read data sequence thus provided, the memory controller sweeps the data strobe signal over a given delay range to determine a delay offset or a range of delay offset values where the expected read data sequence can be captured. After obtaining the appropriate delay offset values, the memory controller then writes to the predefined register to cause the memory device to exit the training mode. After exiting the training mode, the memory device can then resume normal operation with writing and reading data to and from the memory cell array.